1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and particularly to a checking and analyzing technique for a semiconductor integrated circuit.
2. Description of the Related Art
FIGS. 1A through 1C are schematic diagrams each showing a semiconductor integrated circuit 300. FIG. 1A shows a schematic configuration of a semiconductor substrate (which will also be referred to as a “chip” or “die”) 302 on which circuit elements are formed in a pre-processing step. The semiconductor substrate 302 has: an element formation region 302a in which circuit elements such as transistors, wiring patterns, resistors, and the like are integrated; and an I/O region 302b configured as an outer edge portion of the semiconductor substrate 302 in which multiple I/O pads 304 are formed.
FIG. 1B shows the semiconductor integrated circuit 300 in a post-processing step. The semiconductor substrate 302 is mounted (by means of die bonding) on an island 309. Each of the I/O pads 304 of the semiconductor integrated circuit 300 is electrically connected to a corresponding lead terminal (pin) 308 via a bonding wire 310. After the wire bonding step, the semiconductor integrated circuit 300 is sealed by means of resin 312. The semiconductor integrated circuits 300 that operate normally are selected in an electrical characteristics check step, and the normal semiconductor integrated circuits 300 thus selected are shipped.
In recent years, accompanying advances in the multi-functionalization and circuit density of the semiconductor integrated circuit 300, the number of electrical characteristics to be checked in the check step has been steadily increasing. However, the number of lead terminals 308 (the number of leads) is limited. Accordingly, it is difficult to check all the characteristics after mold sealing.
In order to solve such a problem, as shown in FIGS. 1A and 1B, the semiconductor substrate 302 is provided with check pads 306 in addition to the I/O pads 304. Each check pad 306 is connected to a node included in the semiconductor substrate 302, which is to be checked but is not connected to any I/O pad 304. For example, the semiconductor substrate 302 includes, as a built-in component, a reference voltage source 303 configured as a bandgap reference circuit or the like. With such an arrangement, an output node of the reference voltage source 303 is connected to such a check pad 306.
In the wafer check step before the packaging step, a probe is applied such that it is in contact with a corresponding check pad 306. Such an arrangement allows the voltage VREF of the reference voltage source 303 to be checked. Instead of increasing the number of lead terminals 308, by increasing the number of check pads 306, such an arrangement allows a great number of electrical characteristics to be checked.
As a result of investigating such a semiconductor integrated circuit 300 shown in FIG. 1, the present inventors have come to recognize the following problem.
After the semiconductor integrated circuit 300 is shipped as a normal product, in some cases, a defect or a malfunction occurs. Also, after judgment is made in the wafer check step that the semiconductor integrated circuit 300 operates normally, in some cases, judgement is made that it is defective in a test after the assembly step.
However, after the mold sealing, the check pads 306 cannot be accessed. Such an arrangement limits the analysis of the semiconductor integrated circuit 300, which is a problem. It should be noted that such a problem is by no means within the scope of common and general knowledge of those skilled in this art.